This invention relates generally to integrated circuits and more particularly to on-chip inductors.
As is known, wireless communication standards place stringent requirements on wireless communication devices"" dynamic range of operation to accommodate for the dramatic variations in signal strength of receive signals, which may vary by orders of magnitude. To meet these requirements, wireless communication devices are designed using radio frequency (RF) integrated circuits (IC) that consume low power and produce little noise. As is also known, on-chip inductors are significant components of RFIC""s and are used in oscillators, impedance matching networks, emitter degeneration circuits, filters, and/or baluns. Thus, it is desirable to use on-chip inductors that consume as little power as possible and produce as little noise as possible. In addition, it is desirable to use on-chip inductors that provide a desired inductance value at a desired operating rate consuming as little IC real estate as possible.
To minimize power consumption and to reduce noise, an inductor should have a high quality factor (Q factor). As is known, the Q factor is a measure of an inductor""s performance characteristics expressed in power capabilities at a resonant frequency and its selectivity (i.e., power ratio in decibels versus frequency). As is known, CMOS on-chip inductors have a relatively low Q factor in the range of 5-10.
As with any circuit or component implemented on an integrated circuit, the circuit and/or component should be as small as possible (i.e., have as small of an IC footprint as possible) and still be able to achieve the desired performance criteria. In general, on-chip inductors"" performance criteria is becoming more and more demanding as the demands for larger inductance values, high Q factors, lower noise levels, higher operating rates, et cetera increase.
FIG. 1 illustrates a single ended multi-layer on-chip inductor, which includes multiple windings (Windings #1-#3) on multiple layers (Layers #1-#3). As shown, the windings are connected by vias (Vias #1 and #2). While such an inductor provides a relatively small footprint and can have higher inductance values than single layer inductors of a similar footprint, it typically has a relatively significant capacitance value that limits the resonant frequency, which in turn limits the operating frequency of the inductor. In addition and as is generally known, single ended circuits are inherently noisier than differential circuits. Thus, for noise sensitive circuits, a differential inductor is often chosen over a single ended inductor.
FIG. 2 illustrates a single layered differential inductor having 1st and 2nd windings (Windings #1 and #2) on one layer (Layer #1). Winding #1 is coupled to Winding #2 via a bridge on Layer #2 and interconnecting vias #1 and #2. The differential single layered inductor receives a differential signal via nodes 1 and 2. Such a differential inductor has a low capacitance value, but to achieve a large inductance value, it consumes a significant amount of IC real estate. In addition, the differential inductor is not symmetrical because node #1 to ground is all on the first layer and node #2 to ground includes the bridge and the vias, thus it is longer.
Therefore a need exists for a differential inductor that minimizes the use of integrated circuit real estate, can operate at relatively high frequencies, has a relatively high Q factor and a need also exists for a method of design and a method of manufacture for a multi layer differential inductor.
The on-chip differential multi-layer inductor disclosed herein substantially meets these needs and others. Such an on-chip differential multi-layer inductor includes a 1st partial winding on a 1st layer, a 2nd partial winding on the 1st layer, a 3rd partial winding on a 2nd layer, a 4th partial winding on the 2nd layer, and an interconnecting structure. The 1st and 2nd partial windings on the 1st layer are operably coupled to receive a differential input signal. The 3rd and 4th partial windings on the 2nd layer are each operably coupled to a center tap. The interconnecting structure couples the 1st, 2nd, 3rd and 4th partial windings such that the 1st and 3rd partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2nd and 4th partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined. Having determined the electrical parameters of the multi layer established, the geometric shapes of the windings, number of windings, number of layers to support the inductor, and the interconnecting structure may be determined.
Other embodiments of an on-chip differential multi-layer inductor include parallel partial windings on 3rd and 4th layers that are operably coupled in parallel (i.e., shunted) with the 1st, 2nd, 3rd and 4th partial windings. In addition, the positioning of the partial windings with respect to the parallel windings and with respect to each other may be positioned to tune the capacitance value of the inductor to set the resonant frequency at a desired value.
In another aspect of an on-chip differential multi-layer inductor, the windings on multiple layers may have similar metalization (i.e., have about the same amount of metal layers). The amount of metalization, the geometric shape of the windings, and the number of layers to use may be determined based on the desired inductance value, desired metalization coverage, and operating rates. By evenly distributing or near evenly distributing metalization amongst the layers, the manufacturing yield of integrated circuits including on-chip inductors is increased.
As such, multiple embodiments of a differential inductor may be designed and manufactured to minimize the use of integrated circuit real estate, to operate at relatively high frequencies, and to have a relatively high Q factor.